It is desirable to pipe-line the logic in an integrated circuit (IC) for improving the bandwidth of the operation and enable faster clocking of the design. Pipeline of a given logical operation comprises of storage elements called flip-flops that hold value for a full clock cycle or latches that hold value for half clock cycle to store intermediate results. Latches are used in pair per clock cycle stage to hold the information during positive and negative half of a clock cycle. These results are used in next clock cycle by subsequent stages. Pipe-lining an operation reduces the time for each stage of operation and helps improve the clock frequency of the design. This application described the technique of pipe-lining the Clock Guided Logic (CGL) gates using latches. FIG. 1 shows an example circuit constructed as per the teachings of prior art Clock Guided Logic. In FIG. 1, gates 110-1, 110-2, 110-3, 110-4, 110-5, 110-6, and so on, 110-N are CGL elements. In FIG. 1 gates 110-1 and 110-5 EVH type gates; gate 110-3 is an EVL type gate and gates 110-2, 110-4, 110-6 are REG type gates. The example circuit shown in FIG. 1 uses guide signals 130-1, 130-2, 130-3, and so on, 130-M to drive the evaluate and pre-charge phases of the Clock Guided Logic. Guide signals 130-1 and 130-3 drive an EVH type gate while guide signal 130-2 drives an EVL type gate as shown in the CGL example in FIG. 1. The technique described in this application utilizes latching elements to store the intermediate evaluated values of certain nodes of the CGL design while the corresponding CGL circuits that drive the nodes undergo pre-charge phase The latch based pipe-lining technique of this application allows a continuous flow of data to be fed to the inputs of the Clock Guided Logic designs every clock cycle for evaluation thereby increasing the throughput of the pipe-lined design. The art of Clock Guided Logic is described in U.S. Pat. Nos. 7,724,036 B2 and 8,102,189 B2 and description of the prior art Clock Guided Logic technique is incorporated in this application by reference.